Silicon on insulator

For silicon on insulator optical devices, see silicon photonics.

Silicon on insulator (SOI) technology refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improving performance.[1] SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are called silicon on sapphire, or SOS, and are less common). The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon dioxide preferred for improved performance and diminished short channel effects in microelectronics devices.[2] The insulating layer and topmost silicon layer also vary widely with application.[3] The first industrial implementation of SOI was announced by IBM in August 1998.[4]

Contents

Industry need

The implementation of SOI technology is one of several manufacturing strategies employed to allow the continued miniaturization of microelectronic devices, colloquially referred to as extending Moore's Law. Reported benefits of SOI technology relative to conventional silicon (bulk CMOS) processing include[5]:

From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10–15% increase to total manufacturing costs.[6]

Manufacture of SOI wafers

SiO2-based SOI wafers can be produced by several methods:

An exhaustive review of these various manufacturing processes may be found in reference [1]

Use in the microelectronics industry

IBM began to use SOI in the high-end RS64-IV "Istar" PowerPC-AS microprocessor in 2000. Other examples of microprocessors built on SOI technology include AMD's 130 nm, 90 nm, 65 nm and 45 nm single, dual, quad and six core processors since 2001.[15] Freescale adopted SOI in their PowerPC 7455 CPU in late 2001, currently Freescale is shipping SOI products in 180 nm, 130 nm, 90 nm and 45 nm lines.[16] The 90 nm Power Architecture based processors used in the Xbox 360, PlayStation 3 and Wii use SOI technology as well. Competitive offerings from Intel, however, such as the 65 nm Core 2 and Core 2 Duo microprocessors, are built using conventional bulk CMOS technology. Intel's new 45 nm process will continue to use conventional technology. In January, 2005 Intel researchers reported on an experimental single-chip silicon rib waveguide Raman laser built using SOI.[17]

In November 2010, several news sources indicated that Intel may switch to SOI for the 22 nm node.[18]. More recently, Intel announced it will NOT go to SOI at 22nm due to costs, and instead will use tri-gate technology.

On the foundry side, July 2006 TSMC claimed no customer wanted SOI,[19] but Chartered Semiconductor devoted a whole fab to SOI.[20]

Use in photonics

SOI wafers are widely used in silicon photonics.[21] The crystalline silicon layer on insulator can be used to fabricate optical waveguides and other passive optical devices for integrated optics. The crystalline silicon layer is sandwiched between the buried insulator (Silicon oxide, Sapphire etc.) and top cladding of air (or Silicon oxide or any other low refractive index material). This enables propagation of electromagnetic waves in the waveguides on the basis of total internal reflection.

See also

References

  1. ^ a b Celler, G.K., Cristoloveanu, S. J App Phys, 93, 4955 (2003)
  2. ^ SOI design: analog, memory and digital techniques by Andrew Marshall & Sreedhar Natarajan
  3. ^ "Silicon-on-Insulator Technology: Materials to VLSI" by Jean-Pierre Colinge, Springer Verlag, 1991, ISBN 978-0-7923-9150-0.
  4. ^ IBM Advances Chip Technology With Breakthrough For Making Faster, More Efficient Semiconductors
  5. ^ Silicon-on-insulator - SOI technology and ecosystem - Emerging SOI applications by Horacio Mendez, Executive Director of the SOI Industry Consortium, April 9, 2009
  6. ^ IBM touts chipmaking technology
  7. ^ U.S. Patent 5,888,297 Method of fabricating SOI substrate Atsushi Ogura, Issue date: Mar 30, 1999
  8. ^ U.S. Patent 5,061,642 Method of manufacturing semiconductor on insulator Hiroshi Fujioka, Issue date: Oct 29, 1991
  9. ^ SIMOX-SOI Technology: Ibis Technology
  10. ^ "SemiConductor Wafer Bonding: Science and Technology" by Q.-Y. Tong & U. Gösele, Wiley-Interscience, 1998, ISBN 978-0471574811
  11. ^ U.S. Patent 4,771,016 Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor, George Bajor et al., Issue date: Sep 13, 1988
  12. ^ http://www.sigen.com/
  13. ^ ELTRAN - Novel SOI Wafer Technology, JSAPI vol.4
  14. ^ U.S. Patent 5,417,180
  15. ^ Chip Architect: Intel and Motorola/AMD's 130 nm processes to be revealed
  16. ^ Process Technology
  17. ^ Rong, Haisheng (01 2005). "Letters to Nature - An all-silicon Raman laser". Nature 433: 292–294. doi:10.1038/nature03723. http://techresearch.intel.com/spaw2/uploads/files/R817-nature03273.pdf. 
  18. ^ http://www.eetimes.com/electronics-news/4210354/Analyst--Intel-to-endorse-SOI-at-22-nm-semiconductor
  19. ^ TSMC has no customer demand for SOI technology - Fabtech - The online information source for semiconductor professionals
  20. ^ Chartered expands foundry market access to IBM's 90nm SOI technology
  21. ^ "Silicon photonics: an introduction" by Graham T. Reed, Andrew P. Knights. WIley. Page 111

External links